Packaging of chips is an important step in microelectronic fabrication, contributing to the overall cost, performance and reliability of a packaged chip. Some chip boding technologies utilize a copper bump formed on a chip to connect the chip to a package or PC board. For example, a copper bump may be utilized in wafer-level chip-scale packaging (WLCSP) technologies such as flip-chip. In a conventional manufacturing sequence, the chip passivation layer is formed prior to creation of the copper bump.